1. Field of the Invention
The present invention generally relates to multi-spectral defect inspection for 3D wafers.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Semiconductor memory manufacturers, particularly Flash memory now and DRAM in the near future, have had trouble extending their shrinking design rule roadmap to smaller dimensions due to rapidly increasing costs for lithography and multiple process steps associated with pitch splitting techniques. The concept of going vertical has taken off with 3D or VNAND memory leading the way by building transistors (bits) vertically rather than orienting them in a planar manner which historically has been the rule. Early VNAND devices have 16 to 24 vertical bits with roadmaps quickly extending to 48 and 64 bits vertically and beyond. The changes are achieved with fewer process steps, relaxed lithography sizes, and lower manufacturing costs compared with the planar approach; hence, they're being quickly adopted.
The deposition of these thick stacks typically occurs in a single process step with subsequent processing on the whole stack to create the vertical transistors and connections. Wafer inspection for defects needs then to inspect the whole stack. For wafer inspection, these changes result in much thicker stacks of materials and structures, with the early VNAND devices having 2 um to 3 um thick stacks and eventual stacks in the 6 um to 8 um range (typical planar thicknesses are about 0.1 um to 1 um depending upon the process step). Defects in the processing steps can occur throughout these stacks and need to be detected and their source identified and corrected to ensure high manufacturing yields.
Accordingly, it would be advantageous to develop methods and systems for detecting defects in one or more structures on a wafer that have characteristics described above.